1. Field of the Invention
The present invention relates to static type semiconductor memory devices (hereinafter, referred to as "SRAMs"), and more particularly to an SRAM having a plurality of contact holes.
2. Description of the Background Art
Recently, energy saving and lower voltage operation of semiconductor devices which are contained in a portable apparatus have become important to increase the durability of a battery in the portable apparatus. Thus, the demand for SRAMs capable of lower voltage operation at lower power consumption is increasing. In general, an SRAM memory cell for lower voltage operation is formed of six transistors and a full CMOS type memory cell is usually employed.
FIG. 18 is an equivalent circuit diagram of a conventional SRAM memory cell. Referring to FIG. 18, an SRAM memory cell 600 includes n-type driver transistors 642, 645, p-type load transistors 643, 646, and n-type access transistors 641, 646.
Memory cell 600 is connected to bit lines 651, 656, a word line 661, a power supply node 655, and ground nodes 653, 658. In SRAM memory cell 600, a flip-flop circuit is formed of driver transistors 642, 645 and load transistors 643, 646.
Load transistor 643 has its source region connected to power supply node 655 through a contact hole 625 and its drain region connected to a storage node 663 through a contact hole 624. The gate electrode of load transistor 643 is connected to a storage node 662.
Load transistor 646 has its source region connected to power supply node 655 through a contact hole 630 and its drain region connected to storage node 662 through a contact hole 629. The gate electrode of load transistor 646 is electrically connected to storage node 663.
Driver transistor 642 has its source region connected to ground node 653 through a contact hole 623 and its drain region connected to storage node 663 through a contact hole 622. The gate electrode of driver transistor 642 is connected to storage node 662.
Driver transistor 645 has its source region connected to ground node 658 through a contact hole 628 and its drain region connected to storage node 662 through a contact hole 627. The gate electrode of driver transistor 645 is connected to storage node 663.
The gate electrode of access transistor 641 is connected to word line 661. Access transistor 641 has one source/drain region connected to bit line 651 through a contact hole 621 and the other source/drain region connected to storage node 663 through contact hole 622.
The gate electrode of access transistor 644 is connected to word line 661. Access transistor 644 has one source/drain region connected to bit line 656 though a contact hole 626 and the other source/drain region connected to storage node 662 through contact hole 627.
In the following, a plan view of the conventional SRAM memory cell shown in FIG. 18 will be described with reference to FIG. 19. Referring to FIG. 19, SRAM memory cell 600 includes a pair of load transistors 643, 646, a pair of driver transistors 642, 645, and a pair of access transistors 641, 644.
Access transistor 641 is formed of a pair of n-type impurity regions formed in an active region 601 as well as a gate electrode 661. One of the impurity regions is connected to bit line 651 through contact hole 621, and the other impurity region is connected to a storage node 652 through contact hole 622.
Access transistor 644 is formed of a pair of n-type impurity regions formed in an active region 602 as well as gate electrode 661. One of the impurity regions is connected to bit line 656 through contact hole 626, and the other impurity region is connected to a storage node 657 through contact hole 627 and to a gate electrode 662.
Driver transistor 642 is formed of a pair of n-type impurity regions formed in active region 601 as well as gate electrode 662. One of the impurity regions is connected to ground node 653 through contact hole 623, and the other impurity region is connected to storage node 652 through contact hole 622.
Driver transistor 645 is formed of a pair of n-type impurity regions formed in active region 602 as well as a gate electrode 663. One of the impurity regions is connected to ground node 658 through contact hole 628, and the other impurity region is connected to storage node 657 through contact hole 627 and to gate electrode 662.
Load transistor 643 is formed of a pair of p-type impurity regions formed in an active region 603 as well as gate electrode 662. One of the impurity regions is connected to storage node 652 through contact hole 624 and to gate electrode 663, and the other impurity region is connected to power supply node 655 through contact hole 625.
Load transistor 646 is formed of a pair of impurity regions formed in an active region 604 as well as gate electrode 663. One of the impurity regions is connected to storage node 657 through contact hole 629, and the other impurity region is connected to power supply node 655 through contact hole 630.
FIG. 20 shows a section along line XX--XX in FIG. 19. Referring to FIG. 20, an isolation oxide film 670 is formed on a silicon substrate 600a. At the main surface of silicon substrate 600a, n-type impurity regions 601b, 601c, 602a, and 602b are formed. Impurity regions 601b, 601c are formed in active region 601 in FIG. 19, and impurity regions 602a, 602b are formed in active region 602 in FIG. 19.
Between impurity regions 601b and 601c, gate electrode 662 is formed on silicon substrate 600a with a gate oxide film 662a therebetween. Between impurity regions 602a and 602b, gate electrode 663 is formed on the surface of silicon substrate 600a with a gate oxide film 663a therebetween. Further, gate electrode 662 is formed on impurity region 602b with a gate oxide film 662a therebetween.
An interlayer insulation film 681 is formed to cover silicon substrate 600a. In interlayer insulation film 681, contact hole 623 which reaches impurity region 601c, contact hole 622 which reaches impurity region 601b, contact hole 627 which reaches gate electrode 662, and contact hole 628 which reaches impurity region 602a are formed.
In contact holes 623, 622, 627, and 628, a pad electrode 653a, storage nodes 652, 657, and a pad electrode 658a are respectively formed. An interlayer insulation film 682 is formed on interlayer insulation film 681. In interlayer insulation film 682, contact holes 682a, 682b which reach pad electrodes 653a, 658a are formed. Ground nodes 653, 658 are formed to fill contact holes 682a, 682b. Further, bit lines 651, 656 are formed on interlayer insulation film 682.
FIG. 21 shows a section along line XXI--XXI in FIG. 19. Referring to FIG. 21, n-type impurity regions 601a, 601b are formed at the surface of silicon substrate 600a. Impurity regions 601b, 601c are formed in active region 601 in FIG. 19. Between impurity regions 601b and 601c, gate electrode 661 is formed on silicon substrate 600a with a gate oxide film 661a therebetween.
Gate electrodes 662, 663 are formed on isolation oxide film 670. Gate electrode 663 is formed on a p-type impurity region 603a with gate oxide film 663a therebetween.
Interlayer insulation film 681 is formed to cover silicon substrate 600a. In interlayer insulation film 681, contact holes 621, 622, and 624 which reach impurity regions 601a, 601b, and 603a are formed.
A pad electrode 651a is formed to fill contact hole 621. Storage node 652 is formed to fill contact holes 622, 624 and to cover part of the surface of interlayer insulation film 681.
Interlayer insulation film 682 is formed to cover pad electrode 651a and storage node 652. A contact hole 682c which reaches pad electrode 651a is formed in interlayer insulation film 682. Bit line 651 is formed to fill contact hole 682c.
In the following, a method of manufacturing the SRAM shown in FIGS. 19 to 21 will be described. FIGS. 22 to 25 show a manufacturing process of the SRAM shown in FIGS. 19 to 21, in which FIGS. 22 and 24 correspond to the section shown in FIG. 20 and FIGS. 23 and 25 correspond to the section shown in FIG. 21.
Referring to FIGS. 22 and 23, isolation oxide film 670 is formed at the surface of silicon substrate 600a. On silicon substrate 600a, gate electrodes 661, 662, and 663 are formed with gate oxide films 661a, 662a, and 663a therebetween.
Impurity regions 601a, 601b, 601c, 602a, and 602b are formed by implanting n-type impurity ions into silicon substrate 600a. Impurity region 603a is formed by implanting p-type impurity ions into silicon substrate 600a.
Interlayer insulation film 681 is formed to cover silicon substrate 600a. A resist 671 is applied on interlayer insulation film 681. A photo mask 674 with formed contact hole patterns is positioned on resist 671. Photo mask 674 is formed of glass 674a which is transparent to light and a metallic film 674b which is not transparent to light. Light is emitted from the direction denoted by arrow 675 to resist 671 through photo mask 674. Thus, the light passes though a portion of photo mask 674 without metallic film 674b and exposes the underlying resist, thereby causing an exposed portion 672.
Referring to FIGS. 24 and 25, exposed resist 671 is dipped in a developing solution. Thus, exposed portion 672 is removed to form a contact hole pattern.
Referring to FIGS. 20 and 21, interlayer insulation film 681 is selectively etched according to the resist with formed contact hole patterns, and thus contact holes 621, 622, 623, 624, 627, and 628 are formed. Pad electrodes 651a , 653a, 658a and storage nodes 652, 657 are formed to fill these contact holes. Interlayer insulation film 682 is formed on interlayer insulation film 681. Contact holes 682a, 682b, and 682c are formed in interlayer insulation film 682. Ground nodes 653, 658 are formed to fill contact holes 682a, 682b, and 682c, and at the same time bit lines 651, 656 are formed. The SRAM shown in FIGS. 20 and 21 is completed in this manner.
In the following, problems caused by the conventional manufacturing process will be described. FIGS. 26 to 31 are views for describing one problem caused by the conventional manufacturing process. Here, FIGS. 26, 28, and 30 correspond to the section shown in FIGS. 22 and 24 while FIGS. 27, 29, and 31 correspond to the section shown in FIGS. 23 and 25.
Referring to FIGS. 26 and 27, the resist is exposed by light which has passed through photo mask 674. The light passes through resist 671 and is irregularly reflected by underlying silicon substrate 600a, gate electrodes 661, 662, and so on. The surface of a gate electrode has a gate electrode protection film such as a refractory metal silicide film and a silicon nitride film, and therefore especially the surface easily causes irregular reflection. The resist is also exposed by the irregularly reflected light.
As semiconductor devices are miniaturized and their contact holes come to have a diameter of 0.3 .mu.m and an interval of 0.5 .mu.m or less between them, light energy for exposing a resist becomes higher.
If some region has a smaller distance between contact holes compared with other regions, light emitted to a portion for forming a contact hole is reflected by silicon substrate 600a, gate electrodes 611, 622, and the like in the region. Thus, portions 672a, 672b which should not be exposed are eventually exposed. As a result, two adjacent exposed portions 672 are connected.
Referring to FIGS. 28 and 29, when the resist is developed, not only exposed portion 672 which should be exposed but portions 672a, 672b which should have the remaining resist are developed and stripped of the resist. Thus, resist 671 does not exist even in a portion without any contact hole formed.
Referring to FIGS. 30 and 31, when interlayer insulation film 681 is etched by using the above described resist as a mask, interlayer insulation film 681 is etched between contact holes 622 and 627 and between contact holes 621 and 622, thereby connecting two contact holes.
FIG. 32 is a view for describing another problem caused by the conventional manufacturing process. Referring to FIG. 32, when light 675 passes through photo mask 674, exposure is found not only immediately under a region without metallic film 674b but immediately under a region with metallic film 674b. This is caused by light diffraction (Fraunhofer diffraction).
If the distance between contact hole pattern openings 674c assumes a described value in photo mask 674 for contact holes, diffracted light beams which have passed through openings 674c may be overlapped. In this case, the intensity of the diffracted light beams corresponds to curve 698 plus curve 699 which indicate the intensity of secondary diffracted light as shown in FIG. 32. Therefore, this portion is also exposed intensely. As a result, not only exposed portion 672 which is to be exposed but portion 672c which is not to be exposed is exposed in resist 671. When the resist is developed, the resist is removed even in exposed portion 672c and a contact hole is formed in that portion by a subsequent process.